diff -aur gcc-20020722.orig/config-ml.in gcc-20020722/config-ml.in
--- gcc-20020722.orig/config-ml.in	Thu Jul 25 09:32:28 2002
+++ gcc-20020722/config-ml.in	Thu Jul 25 09:34:45 2002
@@ -447,6 +447,17 @@
 	    esac
 	  done
 	fi
+	if [ x$enable_ppc405cpu != xyes ]
+	then
+	  old_multidirs="${multidirs}"
+	  multidirs=""
+	  for x in ${old_multidirs}; do
+	    case "$x" in
+	      *ppc405* ) : ;;
+	      *) multidirs="${multidirs} ${x}" ;;
+	    esac
+	  done
+	fi
 	if [ x$enable_powerpcos = xno ]
 	then
 	  old_multidirs="${multidirs}"
diff -aur gcc-20020722.orig/gcc/config/rs6000/rs6000.h gcc-20020722/gcc/config/rs6000/rs6000.h
--- gcc-20020722.orig/gcc/config/rs6000/rs6000.h	Thu Jul 25 09:32:21 2002
+++ gcc-20020722/gcc/config/rs6000/rs6000.h	Thu Jul 25 09:34:45 2002
@@ -66,7 +66,7 @@
 %{mcpu=rsc1: -D_ARCH_PWR} \
 %{mcpu=401: -D_ARCH_PPC} \
 %{mcpu=403: -D_ARCH_PPC} \
-%{mcpu=405: -D_ARCH_PPC} \
+%{mcpu=405: -D_ARCH_PPC -D__PPC405__} \
 %{mcpu=505: -D_ARCH_PPC} \
 %{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \
 %{mcpu=602: -D_ARCH_PPC} \
diff -aur gcc-20020722.orig/gcc/config/rs6000/t-ppcos gcc-20020722/gcc/config/rs6000/t-ppcos
--- gcc-20020722.orig/gcc/config/rs6000/t-ppcos	Thu Jul 25 09:32:21 2002
+++ gcc-20020722/gcc/config/rs6000/t-ppcos	Thu Jul 25 09:34:45 2002
@@ -1,7 +1,7 @@
 # Multilibs for a powerpc hosted ELF target (linux, SVR4)
 
-MULTILIB_OPTIONS	= msoft-float
-MULTILIB_DIRNAMES	= nof
+MULTILIB_OPTIONS	= msoft-float/mcpu=405
+MULTILIB_DIRNAMES	= nof ppc405
 MULTILIB_EXTRA_OPTS	= fPIC mstrict-align
 MULTILIB_EXCEPTIONS	= 
 
diff -aur gcc-20020722.orig/gcc/doc/install.texi gcc-20020722/gcc/doc/install.texi
--- gcc-20020722.orig/gcc/doc/install.texi	Thu Jul 25 09:32:21 2002
+++ gcc-20020722/gcc/doc/install.texi	Thu Jul 25 09:34:45 2002
@@ -607,9 +607,17 @@
 
 @item powerpc*-*-*, rs6000*-*-*
 aix64, pthread, softfloat, powercpu, powerpccpu, powerpcos, biendian,
-sysv, aix.
+sysv, aix, ppc405cpu.
 
 @end table
+  
+@item --enable-ppc405cpu
+Powerpc only.  Normally, building gcc for powerpc produces normal
+libraries in lib, and @option{-msoft-float} libraries in lib/nof.
+Giving the @option{--enable-ppc405cpu} option causes another set of
+libraries to be produced in lib/ppc405.  These libraries are the same as
+the libraries in nof, except that they also contain a workaround
+for the erratum in the ppc405 stwcx instruction.
 
 @item --enable-threads
 Specify that the target
diff -aur gcc-20020722.orig/libjava/sysdep/powerpc/locks.h gcc-20020722/libjava/sysdep/powerpc/locks.h
--- gcc-20020722.orig/libjava/sysdep/powerpc/locks.h	Thu Jul 25 09:32:30 2002
+++ gcc-20020722/libjava/sysdep/powerpc/locks.h	Thu Jul 25 11:39:13 2002
@@ -11,6 +11,17 @@
 #ifndef __SYSDEP_LOCKS_H__
 #define __SYSDEP_LOCKS_H__
 
+#ifdef __PPC405__
+// workaround for PPC405 erratum #77 - 07/18/02 JRO, dank, NN.  References:
+// http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/89DED00DEBFF54BF87256A8000491BA2/$file/405CR_C_errata_1_2.pdf
+// http://ppc.bkbits.net:8080/linuxppc_2_4_devel/cset@1.489
+// http://www.kegel.com/xgcc3/ppc405erratum77.html
+// FIXME: using dbct instead of sync would be faster
+#define __LIBGCJ_PPC405_ERR77_SYNC   "sync \n\t"
+#else
+#define __LIBGCJ_PPC405_ERR77_SYNC
+#endif
+
 typedef size_t obj_addr_t;	/* Integer type big enough for object	*/
 				/* address.				*/
 
@@ -25,6 +36,7 @@
 	   "0:    lwarx %0,0,%1 ;"
 	   "      xor. %0,%3,%0;"
 	   "      bne 1f;"
+  	  __LIBGCJ_PPC405_ERR77_SYNC
 	   "      stwcx. %2,0,%1;"
 	   "      bne- 0b;"
 	   "1:    "
@@ -58,6 +70,7 @@
 	   "0:    lwarx %0,0,%1 ;"
 	   "      xor. %0,%3,%0;"
 	   "      bne 1f;"
+	   __LIBGCJ_PPC405_ERR77_SYNC	 
 	   "      stwcx. %2,0,%1;"
 	   "      bne- 0b;"
 	   "1:    "
diff -aur gcc-20020722.orig/libstdc++-v3/config/cpu/powerpc/bits/atomicity.h gcc-20020722/libstdc++-v3/config/cpu/powerpc/bits/atomicity.h
--- gcc-20020722.orig/libstdc++-v3/config/cpu/powerpc/bits/atomicity.h	Thu Jul 25 09:32:31 2002
+++ gcc-20020722/libstdc++-v3/config/cpu/powerpc/bits/atomicity.h	Thu Jul 25 09:34:45 2002
@@ -32,6 +32,17 @@
 
 typedef int _Atomic_word;
 
+#ifdef __PPC405__
+// workaround for PPC405 erratum #77 - 07/18/02 JRO & dank.  References:
+// http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/89DED00DEBFF54BF87256A8000491BA2/$file/405CR_C_errata_1_2.pdf
+// http://ppc.bkbits.net:8080/linuxppc_2_4_devel/cset@1.489
+// http://www.kegel.com/xgcc3/ppc405erratum77.html
+// FIXME: using dbct instead of sync would be faster
+#define	__LIBSTDCPP_PPC405_ERR77_SYNC	"sync \n\t"
+#else
+#define __LIBSTDCPP_PPC405_ERR77_SYNC
+#endif
+
 static inline _Atomic_word
 __attribute__ ((__unused__))
 __exchange_and_add (volatile _Atomic_word* __mem, int __val)
@@ -42,6 +53,7 @@
 	"0:\t"
 	"lwarx    %0,0,%2 \n\t"
 	"add%I3   %1,%0,%3 \n\t"
+	__LIBSTDCPP_PPC405_ERR77_SYNC
 	"stwcx.   %1,0,%2 \n\t"
 	"bne-     0b \n\t"
 	"/* End exchange & add */"
@@ -61,6 +73,7 @@
 	"0:\t"
 	"lwarx    %0,0,%1 \n\t"
 	"add%I2   %0,%0,%2 \n\t"
+	__LIBSTDCPP_PPC405_ERR77_SYNC
 	"stwcx.   %0,0,%1 \n\t"
 	"bne-     0b \n\t"
 	"/* End atomic add */"
@@ -78,6 +91,7 @@
 	"/* Inline always swap */\n"
 	"0:\t"
 	"lwarx    %0,0,%1 \n\t"
+	__LIBSTDCPP_PPC405_ERR77_SYNC
 	"stwcx.   %2,0,%1 \n\t"
 	"bne-     0b \n\t"
 	"/* End always swap */"
@@ -98,6 +112,7 @@
 	"lwarx    %0,0,%1 \n\t"
 	"cmpwi    %0,0 \n\t"
 	"bne-     1f \n\t"
+	__LIBSTDCPP_PPC405_ERR77_SYNC
 	"stwcx.   %2,0,%1 \n\t"
 	"bne-     0b \n"
 	"1:\n\t"
